1. Field of the Invention
The present invention relates to a parallel instruction execution type microprocessor, more particularly to an instruction pipeline type microprocessor capable of rapidly executing instructions.
2. Description of the Prior Art
In the instruction pipeline type microprocessor according to the prior art, a particular register or registers are used in order to perform an operand address calculation in, for example an ADD instruction. However, as the content of the register is modified by a previous instruction such as a TRANSFER instruction, the ADD instruction can not be shifted to an operand address calculation stage before a write stage to a general purpose register is terminated, thus delaying the processing of the instruction.
Namely, FIG. 2 shows an outline construction of the instruction pipeline type microprocessor according to the prior art.
In FIG. 2, reference numeral 1 indicates a bus control section (BCU) for connecting a microprocessor P to an external circuit, numeral 2 indicates an instruction fetch section (IFU), 3 indicates a decoder (DEC) for decoding instructions, 4 an operand address calculation section (OAG), 5 an address translation section (AT) for converting a logical address into a physical address, 6 an operand fetch section (OPF) for fetching an operand, 7 an operation execution section (EXU) for executing instructions, 8 general purpose register group (GR) consisting of a plurality of registers R.sub.1, R.sub.2, R.sub.3, R.sub.4, . . . (not indicated).
When machine instructions shown in FIG. 1 are executed by the microprocessor P shown in FIG. 2 for instance, the timing of the instruction pipeline processing becomes the one shown in FIG. 3. As shown in FIGS. 1 and 3, supposing that a.sub.1 is an instruction which transfers the content of an address A to the register R.sub.1 (not indicated) in GR.sub.8, a.sub.2 is an instruction which transfers data in the register R.sub.3 in GR.sub.8 to the register R.sub.2, a.sub.3 is an ADD instruction which transfers the content of an address B which is modified by the register R.sub.2 to the register R.sub.4, and a.sub.4 is an instruction which transfers data in the register R.sub.2 to a memory indicated by address C, the content of the register R.sub.2 is used by the instruction a.sub.3 in order to perform an operand address calculation. However, the content of the register R.sub.2 is modified by the instruction a.sub.2. As a result, the instruction a.sub.3 can not move to OAG.sub.4 until the transfer of the instruction a.sub.2 to GR.sub.8 is terminated, thus delaying the processing of the instruction a.sub.3.
Since the operation execution section and the general purpose register group in the microprocessor according to the prior art are not duplicated, succeeding instructions can be executed only after the instructions for updating the general purpose register group GR.sub.8 have been completely executed.
Accordingly, the advantages of the pipeline system can not be utilized due to stagnation of the processing flow in the instruction pipeline type microprocessors according to the prior art.